T-FLIPFLOP-VERILOG

module tflipflop(clock, reset, t, q);

    input clock;

    input reset;

    input t;

    output q;

             reg q;

always@(posedge clock, negedge reset)

            if(~reset) q=0;

            else if (t)  q=~q;

            else q=q;

endmodule

Modeling of MOSFET using ‘C’.

#include<iostream.h>

#include<stdio.h>

#include<conio.h>

#include<math.h>

//global input variables declaration

float vg, vs,vd,W,L;

//global constant declaration

float Vt=0.6;

float e0=3.45*pow(10,-11);

float Tox=10*pow(10,-9);

float q=1.6*pow(10,-19);

int u=700;

//global variable declaration

float Vgs,Vds,Cox,Beta,Ids;

void main()

{

          W=60*pow(10,-6);

          L=6*pow(10,-6);

          clrscr();

          printf("%e",e0);

          getchar();

          printf("\nModelling of nMOSFET\n");

          printf("\-----------------------\n");

          printf("\n Enter the value of vg:\t");

          scanf("%f",&vg);

          printf("\n Enter the value of vs:\t");

          scanf("%f",&vs);

          printf("\n Enter the value of vd:\t");

          scanf("%f",&vd);

          Vgs=vg-vs;

          Vds=vd-vs;

       printf("==========================\n");

          printf("VGS:\t%f",Vgs);

          printf("\nVDS:\t%f",Vds);

          Cox=e0/Tox;

          printf("\nCox:\t%e",Cox);

          Beta=(u*e0*W)/(Tox*L);

          printf("\nBeta:\t%e", Beta);

          if((Vds>0) && Vds< (Vgs-Vt))

          {

                      printf("\n====================\n");

                      printf("\n NMOS in linear region\n");

                      Ids=Beta*(((Vgs-Vt)*Vds)-((Vds*Vds)/2));

                      printf("\nIds:\t%e",Ids);

          }

          else if((Vgs-Vt)>0 && (Vgs-Vt)<Vds)

          {

                      printf("\n=========================\n");

                      printf("\n NMOS in saturation region\n");

                      Ids=Beta*(((Vgs-Vt)*(Vgs-Vt))/2);

                      printf("\nIds:\t%e",Ids);

          }

          else

          {

                      printf("\n===========================\n");

                      printf("\n NMOS in Cutoff Region\n");

                      Ids=0;

                      printf("\nIds:\t%e",Ids);

          }

          getch();

          }

Implementation of MAC unit-VERILOG

module macunit(a, b, clk,rst, acc);

    input [7:0] a;

    input [7:0] b;

    input clk,rst;

    output [15:0] acc;

           reg [15:0]acc;

           reg [15:0]sum;

           reg [15:0]prod;

reg [15:0]regg;

always @(a,b,clk,rst)

begin

prod=a*b;

sum=prod+regg;

if(rst==1'b1)

begin

regg=0;

end

else

begin

regg=sum;

end

acc=regg;

end

endmodule

JK – Flipflop-VHDL

entity JK_ff is

Port  (   j : in STD_LOGIC;

k : in STD_LOGIC;

clk: in STD_LOGIC;

q: inout STD_LOGIC;

qbar: inout STD_LOGIC);

end JK_ff;                             

architecture Behavioral of JK_ff is

          begin

process (j,k,clk)

begin

if(clk’event and clk=’1’) then

if(j=’0’ and k=’0’) then

q<=q;

qbar<=qbar;

elsif(j=’0’ and k=’1’) then

q<=’0’;

qbar<=’1’;

elsif(j=’1’ and k=’0’) then

q<=’1’;

qbar<=’0’;

elsif(j=’1’ and k=’1’) then

q<=not q;

qbar<= not qbar;

end if;

end if;

                      end process;

end Behavioral;

D-FLIPFLOP-VHDL

entity dflipflop is

    Port ( d : in  STD_LOGIC;

           clk : in  STD_LOGIC;

           rst : in  STD_LOGIC;

           q : out  STD_LOGIC);

end dflipflop;

architecture Behavioral of dflipflop is

begin

process(rst,clk)

                      begin

                                  if(rst='1') then

                                  q<='0';

                                  elsif( clk'event and clk='1') then

                                  q<=d;

                                  end if;

                      end process;

end behavioral;

4-Bit Counter-VERILOG

module rip(c, clr, up_down, q);

    input c;

    input clr;

    input up_down;

    output [3:0] q;

reg [3:0] tmp;

always@(posedge c or  posedge clr)

          begin

          if (clr)

                      tmp = 4'b0000;

          else

                      if (up_down)

                                  tmp = tmp + 1'b1;

                      else

                                  tmp =  tmp - 1'b1;

          end

                                  assign q = tmp;

endmodule

Implementation of ALU-VHDL

entity alu1 is

   Port  (   a : in integer;

 b : in integer;

sel : in BIT_VECTOR (3 downto 0);

c : in BIT_VECTOR (3 downto 0);

d : in BIT_VECTOR (3 downto 0);

y: out integer;

s : out BIT_VECTOR (3 downto 0));

end alu1;

architecture Behavioral of alu1 is

          begin

                      process(a,b,c,d,sel)

                      begin

                                  case sel is

                                  when “0000” => y = a + b;

when “0001” => y = a - b;

when “0010” => s<= c and d;

when “0011” => s< = c nand d;

when “0100” => s<= c sla 1;

when others => y<=0;

end case;

                      end process;

end Behavioral;