Implementation of ALU-VHDL

entity alu1 is

   Port  (   a : in integer;

 b : in integer;

sel : in BIT_VECTOR (3 downto 0);

c : in BIT_VECTOR (3 downto 0);

d : in BIT_VECTOR (3 downto 0);

y: out integer;

s : out BIT_VECTOR (3 downto 0));

end alu1;

architecture Behavioral of alu1 is

          begin

                      process(a,b,c,d,sel)

                      begin

                                  case sel is

                                  when “0000” => y = a + b;

when “0001” => y = a - b;

when “0010” => s<= c and d;

when “0011” => s< = c nand d;

when “0100” => s<= c sla 1;

when others => y<=0;

end case;

                      end process;

end Behavioral;