DESIGN OF REAL TIME CLOCK USING FPGA

DESIGN OF REAL TIME CLOCK USING FPGA

AIM:

To design a real time clock and demonstrate its working on the FPGA board.

   

 APPARATUS REQUIRED:

·        PC

·        xilinx ISE software

   

 PROCEDURE:

·        Open Xilinx ISE software.

·        Open file new project.

·        Enter default data on the dialog box.

·        Select new source from project.

·        Select verilog module.

·        Enter file name.

·        Specify the input & output ports.

·        Type the output syntax.

·        Select implementation constraint file.

·        select file name.

·        Select assign package pins & assign it.

·        Then on the kit & implement the design.

·        In generate program file go to configuration device choose that and close it.

·        Select generate PROM file & click it & generate it.

·        Then go to properties & change CLK to JTAG CLK.

PROGRAM:

module RTC (clk,rst,mode,set,sl,atoh);

input clk; //system clk

input rst;//reset

input [1:0] mode;//mode selection

input [7:0] set;//set value

input [5:0] sl;//segment  selection

output [7:0] atoh;//segment display control data

reg[5:0] sl;

reg[7:0] atoh;

reg[26:0] sig2;

reg[19:1] sig3;

reg[7:0] ssdigit1, ssdigit2, ssdigit3, ssdigit4, ssdigit5, ssdigit6;

reg[3:0] digit1, digit2, digit3, digit4, digit5, digit6;

always @ (posedge clk (or) negedge rst)

begin

if(rst==1’b0)begin

sig1=0;

sig3=0;

digit1=0;

digit2=0;

digit3=0;

digit4=0;

digit5=0;

digit6=0;

end

else begin

if(mode==2’b00) begin // hours

if(set[7:4]<=4’b0010)

digit1=set[7:4];

if(set[3:0]<=4’b1001)

digit2=set[3:0];

else

digit2=0;

end

else if(set[7:4]==4’b0010)begin

if(set[3:0]<=4’b0011)begin

digit1=set[7:4];

digit2=set[3:0];

end

 else begin

digit1=0;

digit2=0;

end

end

else begin

digit1=0;

digit2=0;

end

end

else if(mode==2’b01)begin

if(set[7:4]==4’b0101)

digit3=set[7:4];

if(set[3:0]<=4’b1001)

digit4=set[3:0];

else

digit4=0;

end

else begin

digit3=0;

digit4=0;

end

end

else if(mode==2’b10)begin

if(set[7:4]<=4’b0101)begin

digit5=set[7:4];

if(set[3:0]<=4’b1001)

digit6=set[3:0];

else

digit6=0;

end

else begin

digit5=0;

digit6=0;

end

end

else begin

sig2=sig2+1;

case(sig2[24:23])

2’b00:begin

digit6=digit6+1;

if(digit6>4’b1001)begin

digit6=4’b0000;

digit5=digit5+1;

if(digit5>4’b0101)begin

digit5=4’b0000;

digit4=digit4+1;

if(digit4>4’b1001)begin

digit4=4’b0000;

digit3=digit3+1;

if(digit3>4’b0101)begin

digit3=4’b0000;

digit2=digit2+1;

if(digit2>4’b1001)begin

digit2=4’b0000;

digit1=digit5+1;

end

if((digit1>=4’b0010)&( digit2>=4’b0100))begin

digit1=4’b0000;

digit2=4’b0000;

end

end

end

end

end

sig3=[24:23]=2’b01;

end

2’b11:begin

if(sig2[22:19]==4’b1001)

sig2=0;

end

default:begin

end

end case

end

sig3=sig3+1;

case(sig3[17:15])

3’b000:begin

S1=6’b111110;

Case(digit1)

4’b0000:ssdigit1=8’b00111111;

4’b0001:ssdigit1=8’b00000110;

4’b0010:ssdigit1=8’b01011011;

default:ssdigit1=8’b00000000;

end case

atoh=ssdigit1;

end

3’b001:begin

s1=6’b111101;

case(digit2)

4’b0000:ssdigit2=8’b00111111;

4’b0001:ssdigit2=8’b00000110;

4’b0010:ssdigit2=8’b01011011;

4’b0011:ssdigit2=8’b01001111;

4’b0100:ssdigit2=8’b01100110;

4’b0101:ssdigit2=8’b01101101;

4’b0110:ssdigit2=8’b01111101;

4’b0111:ssdigit2=8’b00000111;

4’b1000:ssdigit2=8’b01111111;

4’b1001:ssdigit2=8’b01101111;

default:ssdigit2=8’b00000000;

end case

atoh=ssdigit2;

end

3’b011:begin

s1=6’b111011;

case(digit3)

4’b0000:ssdigit3=8’b00111111;

4’b0001:ssdigit3=8’b00000110;

4’b0010:ssdigit3=8’b01011011;

4’b0011:ssdigit3=8’b01001111;

4’b0100:ssdigit3=8’b01100110;

4’b0101:ssdigit3=8’b01101101;

default:ssdigit3=8’b00000000;

end case

atoh=ssdigit3;

end

3’b100:begin

s1=6’b110111;

case(digit4)

4’b0000:ssdigit4=8’b00111111;

4’b0001:ssdigit4=8’b00000110;

4’b0010:ssdigit4=8’b01011011;

4’b0011:ssdigit4=8’b01001111;

4’b0100:ssdigit4=8’b01100110;

4’b0101:ssdigit4=8’b01101101;

4’b0110:ssdigit4=8’b01111101;

4’b0111:ssdigit4=8’b00000111;

4’b1000:ssdigit4=8’b01111111;

4’b1001:ssdigit4=8’b01101111;

default:ssdigit4=8’b00000000;

end case

atoh=ssdigit4;

end

3’b110:begin

s1=6’b101111;

case(digit5)

4’b0000:ssdigit5=8’b00111111;

4’b0001:ssdigit5=8’b00000110;

4’b0010:ssdigit5=8’b01011011;

4’b0011:ssdigit5=8’b01001111;

4’b0100:ssdigit5=8’b01100110;

4’b0101:ssdigit5=8’b01101101;

default:ssdigit5=8’b00000000;

end case

atoh=ssdigit5;

end

3’b111:begin

s1=6’b011111;

case(digit6)

4’b0000:ssdigit6=8’b00111111;

4’b0001:ssdigit6=8’b00000110;

4’b0010:ssdigit6=8’b01011011;

4’b0011:ssdigit6=8’b01001111;

4’b0100:ssdigit6=8’b01100110;

4’b0101:ssdigit6=8’b01101101;

4’b0110:ssdigit6=8’b01111101;

4’b0111:ssdigit6=8’b00000111;

4’b1000:ssdigit6=8’b01111111;

4’b1001:ssdigit6=8’b01101111;

default:ssdigit6=8’b00000000;

end case

atoh=ssdigit6;

end

end case

end

end

end module

UCF:

 NET”clk”           LOC=”A8”;

NET”rst”            LOC=”j6”;

NET”atoh<0>” LOC=”p8”;

NET”atoh<1>” LOC=”p10”;

NET”atoh<2>” LOC=”p9”;

NET”atoh<3>” LOC=”p6”;

NET”atoh<4>” LOC=”p8”;

NET”atoh<5>” LOC=”p5”;

NET”atoh<6>” LOC=”p3”;

NET”atoh<7>” LOC=”p11”;

NET”s1<0>”     LOC=”p1”;

NET”s1<1>”     LOC=”p2”;

NET”s1<2>”     LOC=”p7”;

NET”s1<3>”     LOC=”r4”;

NET”s1<4>”     LOC=”r11”;

NET”s1<5>”     LOC=”r18”;

RESULT:

            Thus the design of real time clock is done and its working is verified