lab experiments -STUDY OF SYNTHESIS TOOLS

AIM:

      To study the synthesis tools using HALF ADDER and FULL ADDER gates.

APPARATUS REQUIRED:

      Personal computer

      Xilinx software

PROCEDURE:

·        Open Xilinx Ise software.

·        Open file, New project.

·        Enter default data on dialog box.

·        Select New source from project.

·        Select verilog module.

·        Enter the file name.

·        Specify the input and output port.

·        Type the output syntax.

·        Select source and simulate the behavioural      module.

·        Select New source from project.

·        Select test bench waveform.

·        Give different file name.

·        Initialize the clock information and enable the internal clock.

·        Set the input values and save.

PROGRAM:

HALF ADDER:

        

          module half adder(a,b,c,s);

          Input a;

          Input b;

         Output c;

         Output s;

        assign c=(a&b);

        assign s=(a^b);

        end module

FULL ADDER:

       module full adder(a,b,c,s,ca);

       Input a;

       Input b;

       Input c;

      Output s;

      Output ca;

       assign s=(a^b)^c;

      assign ca=(a&b)|(b&c)|(c&a);

      end module

RESULT:

           Thus the synthesis of  tools using Half and Full adder is obtained and studied.