PARALLEL ADDER AND SUBTRACTOR

PARALLEL  ADDER AND SUBTRACTOR

AIM:

Design and stimulation of pipelined parallel adder and subtractor to add or subtract 8 nos of size 12 bits each in 2’s complement.

APPARATUS REQUIRED:

·        Personal computer

·        Xilinx ISE software

PROCEDURE:

·        Open Xilinx ISE software.

·        Open file new project.

·        Enter default data on the dialog box.

·        Select new source from project.

·        Select verilog module.

·        Enter file name.

·        Specify the input & output ports.

·        Type the output syntax.

·        Select synthesis/implementation in source window.

·        In the process window select synthesis–XST.

·        Select view synthesis report and note down the final report.

·        Select the view RIC schematics and check the block diagram.

·        Select stimulate behavioral model and give the input and output waveforms.

PROGRAM:

A.    PARALLEL ADDER USING 2’S COMPLEMENT:

module padd(sum,carry);

output [11:0]sum;

output [2:0]carry;

reg [11:0]sum;

reg [2:0]carry;

// 8 inputs each.

reg [11:0] in1=12’b000000000001;//001

reg [11:0] in2=12’b000000000001;//001

reg [11:0] in3=12’b000000000001;//001

reg [11:0] in4=12’b000000000001;//001

reg [11:0] in5=12’b000000000010;//002

reg [11:0] in6=12’b000000000010;//002

reg [11:0] in7=12’b000000000010;//002

reg [11:0] in8=12’b000000000010;//002

//Temporary Signals

reg [12:0] temp=13’b1000000000000;

reg [15:0] temp1=16’b1000000000000000;

reg [11:0] a1,a2,a3,a4,a5,a6,a7,a8;

reg [14:0] c=15’b000000000000000;

reg [14:0] res=15’b000000000000000;

always@(temp,in1,in2,in3,in4,in5,in6,in7,in8,temp1,a1,a2,a3,a4,a5,a6,a7,

a8,res,c)

begin

a1<= temp - in1;

a2<= temp - in2;

a3<= temp-in3;

a4<= temp-in4;

a5<= temp-in5;

a6<= temp-in6;

a7<= temp-in7;

a8<= temp-in8;

//Adding all 2’s complement data.

c<=a1+a2+a3+a4+a5+a6+a7+a8;

res<=temp1 - c;

sum<=res[11:0];

carry<=res[14:12];

end

end module

B.    PARALLEL SUBTRACTOR USING 2’S COMPLEMENT:

module psub(res,sign);

output [14:0]res;

output sign;

reg [14:0]res;

reg sign;

// 8 inputs of each 12 bits.

reg [11:0] in1=12’b000000001111;//00F

reg [11:0] in2=12’b000000000001;//001

reg [11:0] in3=12’b000000000001;//001

reg [11:0] in4=12’b000000000001;//001

reg [11:0] in5=12’b000000000001;//001

reg [11:0] in6=12’b000000000001;//001

reg [11:0] in7=12’b000000000001;//001

reg [11:0] in8=12’b000000000001;//001

// Temporary signals.

reg [15:0] temp=16’b1000000000000000;

reg [16:0] temp1=17’b10000000000000000;

reg [14:0] store,p1;

reg [15:0] p2,res1;

always@(temp,in1,in2,in3,in4,in5,in6,in7,in8,temp, p1,p2,res1, store)

begin

store<=in2+in3+in4+in5+in6+in7+in8;

p1<=temp - store;

p2<=in1+p1;

if(p2[15]==1’b1)

res<=p2[14:0];

sign<=1’b0;//no carry

end

else begin

res1<=temp1-p2;

res<=res1[14:0];

sign<=1’b1;//carry

end

end

end module

RESULT:

Thus the parallel adder and subtractor simulation is designed and output is obtained.