TESTING THE TRAFFIC LIGHT CONTROLLER USING FPGA
AIM:
To test the traffic light controller using the FPGA.
APPARATUS REQUIRED:
PC
XILNX ISE software.
THEORY:
Consider a controller for traffic at the intersection of a roads .Consider p1, p2, p3, p4 as 4 roads and pL as pedestrian .The road has the following states.
Green=10011; Yellow=01000; Red=00100
The pedestrian has following states.
Green=0000; Red=1111
First the road p1 is green and all other roads are red .after a delay p1 is turned yellow and then red.p2 is turned green. After a delay p2 is yellow and then red. The p3 becomes green. After a delay p3 becomes yellow and red.p4 becomes green. After a delay it becomes yellow and then red. The pedestrian becomes green after delay and p1 turned to green and routine continues.
PROCEDURE:
· Open Xilinx ISE software.
· Open fileànew project.
· Enter default data on dialog box.
· Select new source from project.
· Enter file name.
· Specify the input and output ports.
· Type the output syntax.
· In process window select Synthesis XST.
· Select new source from project.
· Select implementation constraints file.
· Select file name.
· Select user constraints from dialog box.
· Select assign package pin and assign the pins.
· Then ON the kit and synthesis the implement design and generate programming file.
· Then select the configure device and then choose configure device option and close it.
· Select generate PROM file and choose prepare PROM file and right click to generate PROM file.
· Then right click the generate programming file and go to properties.
· Change the start up clock option to J-TAG clock.
· Then again synthesis it.
· Select configure device and choose configure device using boundary scan and select it.
· Run the program.
· Verify the Output .
PROGRAM:
module tff(clk, reset, p1, p2, p3, p4, pl);
input clk;
input reset;
output [4:0] p1;
output [4:0] p2;
output [4:0] p3;
output [4:0] p4;
output [3:0] pl;
reg [4:0] p1;
reg [4:0] p2;
reg [4:0] p3;
reg [4:0] p4;
reg [3:0] pl;
reg [31:0] sig;
always @(posedge clk or negedge reset)
begin
If (reset==I’bo) begin
p1<=5’b00100;
p2<=5’b00100;
p3<=5’b00100;
p4<=5’b00100;
pl<=4’b1111;
sig<=8’h00000000;
end
else begin
sig<=sig+1;
case(sig [29:24])
6’b000000:begin
p1<=5’b10011;
p2<=5’b00100;
p3<=5’b00100;
p4<=5’b00100;
pl<=4’b1111;
end
6’b000100:begin
p1<=5’b01000;
p2<=5’b00100;
p3<=5’b00100;
p4<=5’b00100;
pl<=4’b1111;
end.
6’b001000:begin
p1<=5’b00100;
p2<=5’b10011;
p3<=5’b00100;
p4<=5’b00100;
pl<=4’b1111;
end.
6’b001100:begin
p1<=5’b00100;
p2<=5’b01000;
p3<=5’b00100;
p4<=5’b00100;
pl<=4’b1111;
end.
6’b010000:begin
p1<=5’b00100;
p2<=5’b00100;
p3<=5’b10011;
p4<=5’b00100;
pl<=4’b1111;
end
6’b010100:begin
p1<=5’b00100;
p2<=5’b00100;
p3<=5’b01000;
p4<=5’b00100;
pl<=4’b1111;
end
6’b011000:begin
p1<=5’b00100;
p2<=5’b00100;
p3<=5’b00100;
p4<=5’b10011;
pl<=4’b1111;
end
6’b100000:begin
p1<=5’b00100;
p2<=5’b00100;
p3<=5’b00100;
p4<=5’b01000;
pl<=4’b0000;
end.
6’b 100100:sig<=8’h00000000;
default: begin
end
end case
end
end
end module
UCF :
NET “CLK” LOC=”A8”
NET”RESEF” LOC=”J6”
NET”P1<0>” LOC=”B14”
NET”P1<1>” LOC=”C16”.
NET”P1<2>”LOC=”D15”.
NET”P1<3>”LOC=”F14”.
NET”P1<4>” LOC=”G14”.
NET”P2<0>”LOC=”G16”.
NET”P2<1>”LOC=”H15”.
NET”P2<2>”LOC=”K15”.
NET”P2<3>”LOC=”F15”.
NET”P3<0>”LOC=”H14”.
NET”P3<1>” LOC=”J16”
NET”P3<2>” LOC=”K16”.
NET”P3<3>”LOC=”M16”.
NET”P3<4>”LOC=”N16”.
NET”P4<0>” LOC=”P16”.
NET”P4<1>”LOC=”R16”.
NET”P4<2>”LOC=”C15”.
NET”P4<3>”LOC=”D14”.
NET”P4<4>”LOC=”E16”.
SNET”PL<0>”LOC=”L15”.
NET”PL<1>” LOC=”N15”
NET”PL<2>” LOC=”P15”.
NET”PL<3>”LOC=”R15”.
RESULT:
Thus the testing of the traffic light controller using FPGA is done and the output is verified.
No comments:
Post a Comment