STUDY OF DEVELOPMENT TOOLS FOR FPGA’S

STUDY OF DEVELOPMENT TOOLS FOR FPGA’S 

AIM:

To study the development tools for FPGA’s

APPARATUS REQUIRED:

·        PC

·        Xilinx ISE software

THEORY:

                        To study the development tool for FPGA Xilinx ISE tool is used. After the place and route step the CLB’s o chip must be configured. To implement the behavior of net list compared that had been mapped to them. This is achieved by determining the values of the configuration bits. Additional bits must be set to realize the routing between configurable logic blocks. This is the process of bit generation. Thus implement design.

PROGRAM:

AND GATE:

module andgate(a,b,c);

input a;

 input b;

output c;

assign c=a&b;

end module

PROCEDURE:

·        Open Xilinx ISE software.

·        Open fileànew project.

·        Enter default data on dialog box.

·        Select new source from project.

·        Enter file name.

·        Specify the input and output ports.

·        Type the output syntax.

·        In process window select Synthesis XST.

·        Select new source from project.

·        Select implementation constraints file.

·        Select file name.

·        Select user constraints from dialog box.

·        Select assign package pin and assign the pins.

·        Then ON the kit and synthesis the implement design and generate programming file.

·        Then select the configure device and then choose configure device option and close it.

·        Select generate PROM file and choose prepare PROM file and right click to generate PROM file.

·        Then right click the generate programming file and go to properties.

·        Change the start up clock option to J-TAG clock.

·        Then again synthesis it.

·        Select configure device and choose configure device using boundary scan and select it.

·        Then put the .bit file into PROM file and .mcb file into another and close it.

·        Then right click and choose program and click OK and run the program.

·        Verify the output.

RESULT:

            Thus the study of development tools is done and the output is verified.