PLACE AND ROOT BACK ANOTATION FOR FPGA

       PLACE AND ROOT BACK ANOTATION FOR FPGA

AIM:

To place and root back anotation for FPGA.

APPARATUS REQUIRED:

·        Personal computer.

·        Xilinx ISE software.

THEORY:

For full adder module we have a gate level net list. The step is to map the design on to the FPGA.The primitive hardware elements that are available in Xilinx, XC3S500E chip namely lookup table and positive edge triggered flip flop are organized as a 2D array of CLB.The netlist from synthesis is compared to gates, latches and flip flops. It is necessary to assign CLB netlist primitives. This is the process of mapping a design. This process effectively translates the gate level netlist produced by the synthesis compiler in to a netlist of a FPGA primitive hardware component. Each elements of this made a new project netlist corresponds to a new hardware primitive in FPGA chip. The map to design produces indicates the set of FPGA hardware primitive and their interconnection. The next step is top assign each of those components in the netlist to a equivalent physical primitive on the FPGA chip. Once this placement is made the interconnection between the components must be made within the chip. This will require route in signals through the switch matrix and other interconnect resources available on FPGA chip. After a place and route the design can be simulated to validate the design.

PROCEDURE:

·        Open Xilinx ISE software.

·        Open file new project.

·        Enter default data on the dialog box.

·        Select new source from project.

·        Select verilog module.

·        Enter file name.

·        Specify the input & output ports.

·        Type the output syntax.

·        Select synthesis/implementation in source window.

·        In the process window select synthesis–XST.

·        Select implementation constraints file name.

·        Select file name.

·        Select user constraints from the processor dialog box.

·        Select assign package pins from the user constraints and save it.

·        Select implement design.

·        Select floorplanner and verify the output.

 PROGRAM FOR FULL ADDER:

module fulladder(s,ca,a,b,c);

input a;

input b;

input c;

output s;

output ca;

assign s= (a^b)^c;

assign ca=(a&b)|(b&c)|(c&a);

end module

          UCF:

NET “a<0>” LOC=”t14”;

NET “b<0>” LOC=”r13”;

NET “c<0>” LOC=”q12”;

NET “s<0>” LOC=”m1”;

NET “d<0>” LOC=”k1”;

RESULT:

Thus the place and root and back notation for FPGA is done and output is verified