B.E-ECE-LAB -STUDY OF SIMULATION TOOLS

STUDY OF SIMULATION TOOLS

AIM:

     To study simulate the tools using AND,OR and NOT gates.

APPARATUS REQUIRED:

      Personal computer

      Xilinx ISE software

PROCEDURE:

·        Open Xilinx Ise software.

·        Open file, New project.

·        Enter default data on dialog box.

·        Select New source from project.

·        Select Verilog module.

·        Enter the file name.

·        Specify the input and output port.

·        Type the output syntax.

·        Select synthesis/implementation  in the source window.

·        In the process window,select synthesis-XST final report.

·        Select view RTL schematics and check the block diagram.

·        Select view technology schematics and check the K-map, truth table and schematic diagram.

PROGRAM:

AND GATE:

module andgate(a,b,c);

Input a;

Input b;

Output c;

assign c=a&b;

endmodule

OR GATE:

module orgate(a,b,c);

Input a;

Input b;

Output c;

assign c=a|b;

endmodule

NOT GATE:

module notgate(a,b);

Input a;

Output b;

assign b=!a;

endmodule

 RESULT:

         Thus the simulation tools are studied and simulated using AND,OR and NOT gates.