SERIAL ADDER AND SUBTRACTOR
AIM:
To design and stimulate the pipelined serial adder and subtractor to add or subtract 8 number of size 12 bits each in 2’s complement.
APPARATUS REQUIRED:
· PC
· Xilinx ISE software
PROCEDURE:
· Open Xilinx ISE software.
· Open file new project.
· Enter default data on the dialog box.
· Select new source from project.
· Select verilog module.
· Enter file name.
· Specify the input & output ports.
· Type the output syntax.
· Select synthesis/implementation in source window.
· In the process window select synthesis–XST.
· Select view synthesis report and note down the final report.
· Select view RTL synthesis the schematic and check the block diagram.
· Select stimulate behavioral modal and give the input and output Waveform.
SERIAL ADDER USING 2’S COMPLEMENT:
module sadd (sum,carry);
output [11:0] sum;
output [2:0] sum;
reg [11:0] sum;
reg[2:0] carry;
//8 input each of 12 bits
reg [11:0] in1=12’b000000000001;// 001
reg [11:0] in 2=12’b000000000001;// 001
reg[11:3] in 3=12’b000000000001;// 001
reg[11:0] in 4=12’b000000000001;// 001
reg[11:0] in 5=12’b000000000010;// 002
reg[11:0] in 6=12’b000000000010;// 002
reg[11:0] in 7=12’b000000000010;// 002
reg[11:0] in 8 12’b000000000010;// 002.
// temporary signals
reg[12:0] a1,a2,a3,a4,a5,a6,a7,a8;
reg[12:0] temp=13’b1000000000000;
reg[15:0] temp1=16’b1000000000000000;
reg[2:0] carry=3’b000;
reg[14:0] c=15’b000000000000000;
reg[14:0] reg=15’b0000000000000000;
reg[13:0]bit0,bit1,bit2,bit3,bit4,bit5,bit6,bit6,bit7,bit8,bit9,bit10,bit11,bit12;
always@(temp,in1,in2,in3,in4,in5,in6,in7,in8,a1,a2,a3,a4,a5,a6,a7,a8,temp1,c, reg, bit0, bit1, bit12)
begin
//CONVERTING INPUT DATA INTO 2’S COMPLEMENT DATA
a1<=temp-in1; //2’s complement of in1
a2<=temp-in2; //2’s complement of in2
a3<=temp-in3; //2’s complement of in3
a4<=temp-in4; // 2’s complement of in4
a5<=temp-in5; //2’s complement of in5
a6<=temp-in6; //2’s complement of in6
a7<=temp-in7; //2’s complement of in7
a8<=temp-in8; //2’s complement of in8.
//ADDING 2’S COMPLEMENT DATA SERIALLY
bit0<=a1[0]+a2[0]+a3[0]+a4[0]+a5[0]+a6[0]+a7[0]+a8[0];
bit1<=a1[1]+a2[1]+a3[1]+a4[1]+a5[1]+a6[1]+a7[1]+a8[1];
bit2<=a1[2]+a2[2]+a3[2]+a4[2]+a5[2]+a6[2]+a7[2]+a8[2];
bit3<=a1[3]+a2[3]+a3[3]+a4[3]+a5[3]+a6[3]+a7[3]+a8[3];
bit4<=a1[4]+a2[4]+a3[4]+a4[4]+a5[4]+a6[4]+a7[4]+a8[4];
bit5<=a1[5]+a2[5]+a3[5]+a4[5]+a5[5]+a6[5]+a7[5]+a8[5];
bit6<=a1[6]+a2[6]+a3[6]+a4[6]+a5[6]+a6[6]+a7[6]+a8[6];
bit7<=a1[7]+a2[7]+a3[7]+a4[7]+a5[7]+a6[7]+a7[7]+a8[7] ; ;
bit8<=a1[8]+a2[8]+a3[8]+a4[8]+a5[8]+a6[8]+a7[8]+a8[8];
bit9<=a1[9]+a2[9]+a3[9]+a4[9]+a5[9]+a6[9]+a7[9]+a8[9];
bit10<=a1[10]+a2[10]+a3[10]+a4[10]+a5[10]+a6[10]+a7[10]+a8[10];
bit11<=a1[11]+a2[11]+A3[11]+a4[11]+a5[11]+a6[11]+a7[11]+a8[11];
bit12<=a1[12]+a2[12]+a3[12]+a4[12]+a5[12]+a6[12]+a7[12]+a8[12];
//CONCANTENATE CARRY AND LOWER BITS
c<={bit12[0],bit11[0],bit10[0],bit9[0],bit8[0],bit7[0],bit6[0],bit5[0],bit4[0],
bit3[0],bit2[0],bit1[0],bit0[0]};
//again 2’s complement the adder data to get original value
reg<=temp1-c;
sum<=reg[11:0];
carry<=reg[14:12];
end
end module.
SERIAL SUBTRACTOR:
module Ssub(reg,sign);
output[14:0] reg;
output sign;
reg[14:0] reg;
reg sign;
//8 INPUTS OF 12 BITS EACH
reg[11:0] in 1=12’b000000001111; //00F
reg[11:0] in 2=12’b000000000001; //001
reg[11:0] in 3=12’b000000000001; //001
reg[11:0] in 4=12’b000000000001; //001
reg[11:0] in 5=12’b000000000001; //001
reg[11:0] in 6=12’b000000000001; //001
reg[11:0] in 7=12’b000000000001; //001
reg[11:0] in 8=12’b000000000001; //001
//TEMPORARY SIGNALS
reg[15:0] temp=16’b100000000000000000;
reg[16:0] temp1=17’b10000000000000000;
reg[3:0] bit0,bit1,bit2,bit3,bit4,bit5,bit6,bit7,bit8,bit9,bit10,bit11;
reg[1:0] bit0,bit1,bit2,bit3,bit4,bit5,bit6,bit7,bit8,bit9,bit10,bit11,bit12,bit13,
bit14;
reg[15:0] c,reg1;
reg[14:0] store,t1;
//ADDING DATA IN 2 TO IN 8 SERIALLY
bit0<=in 2[0]+in 3[0]+in 4[0]+in 5[0]+in 6[0]+in 7[0]+in 8[0];
bit1<=in 2[1]+in 3[1]+in 4[1]+in 5[1]+in 6[1]+in 7[1]+in 8[1]+bit0[3:1];
bit2<=in 2[2]+in 3[2]+in 4[2]+in 5[2]+in 6[2]+in 7[2]+in 8[2]+bit1[3:1];
bit3<=in 2[3]+in 3[3]+in 4[3]+in 5[3]+in 6[3]+in 7[3]+in 8[3]+bit2[3:1];
bit4<=in 2[4]+in 3[4]+in 4[4]+in 5[4]+in 6[4]+in 7[4]+in 8[4]+bit3[3:1];
bit5<=in 2[5]+in 3[5]+in 4[5]+in 5[5]+in 6[5]+in 7[5]+in 8[5]+bit4[3:1];
bit6<=in 2[6]+in 3[6]+in 4[6]+in 5[6]+in 6[6]+in 7[6]+in 8[6]+bit5[3:1];
bit7<=in 2[7]+in 3[7]+in 4[7]+in 5[7]+in 6[7]+in 7[7]+in 8[7]+bit6[3:1]
bit8<=in 2[8]+in 3[8]+in 4[8]+in 5[8]+in 6[8]+in 7[8]+in8[8]+bit7[3:1];
bit9<=in 2[9]+in 3[9]+in 4[9]+in 5[9]+in 6[9]+in 7[9]+in 8[9]+bit8[3:1];
bit10<=in 2[10]+in 3[10]+in 4[10]+in 5[10]+in 6[10]+in 7[10]+in8[10]+bit9[3:1];
bit11<=in 2[11]+in 3[11]+in 4[11]+in 5[11]+in6[11]+in7[11]+in8[11]+bit10[3:1];
//CONCANTENATE CARRY AND LOWER BIT
Store<={bit11[0],bit10[0],bit9[0],bit8[0],bit7[0],bit6[0],bit5[0],bit4[0],bit3[0]
bit2[0],bit1[0],bit0[0]};
p1<=temp-store;
//ADDING DATA IN 1 AND P1 SERIALLY
bits[0]<=in 1[0]+p1[0];
bits[1]<=in 1[1]+in p1[1]+bits0[1];
bits[2]<=in 1[2]+in p1[2]+bits1[1];
bits[3]<=in 1[3]+in p1[3]+bits2[1];
bits[4]<=in 1[4]+p1[4]+bits3[1];
bits[5]<=in 1[5]+p1[5]+bits4[1];
bits[6]<=in 1[6]+p1[6]+bits5[1];
bits[7]<=in 1[7]+p1[7]+bits6[1];
bits[8]<=in 1[8]+p1[8]+bits7[1];
bits[9]<=in 1[9]+p1[9]+bits8[1];
bits[10]<=in 1[10]+p1[10]+bits9[1];
bits[11]<=in 1[11]+p1[11]+bits10[1];
bits[12]<=1’b[0]+p1[12]+bits11[1];
bits[13]<=1’b[0]+p1[13]+bits12[1];
bits[14]<=1’b[0]+p1[14]+bits13[1];
//CONCANTENATE CARRY AND LOWER BITS
C<={bits14,bits13[0],bits12[0],bits11[0],bits10[0],bits9[0],bits8[0],bits7[0],
bits6[0],bits5[0],bits4[0],bits3[0],bits2[0],bits1[0],bits0[0]};
if(c[15]==1’b1)begin
sign=1’b0;
reg<=c[14:0];
end
else begin
sign<=1’b1;
reg1<=temp1-c;
reg<=reg1[14:0];
end
end
end module.
RESULT:
Thus the serial adder and subtractor is designed and simulated.
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