T-FLIPFLOP-VERILOG

module tflipflop(clock, reset, t, q);

    input clock;

    input reset;

    input t;

    output q;

             reg q;

always@(posedge clock, negedge reset)

            if(~reset) q=0;

            else if (t)  q=~q;

            else q=q;

endmodule