JK – Flipflop-VHDL

entity JK_ff is

Port  (   j : in STD_LOGIC;

k : in STD_LOGIC;

clk: in STD_LOGIC;

q: inout STD_LOGIC;

qbar: inout STD_LOGIC);

end JK_ff;                             

architecture Behavioral of JK_ff is

          begin

process (j,k,clk)

begin

if(clk’event and clk=’1’) then

if(j=’0’ and k=’0’) then

q<=q;

qbar<=qbar;

elsif(j=’0’ and k=’1’) then

q<=’0’;

qbar<=’1’;

elsif(j=’1’ and k=’0’) then

q<=’1’;

qbar<=’0’;

elsif(j=’1’ and k=’1’) then

q<=not q;

qbar<= not qbar;

end if;

end if;

                      end process;

end Behavioral;