D-FLIPFLOP-VHDL

entity dflipflop is

    Port ( d : in  STD_LOGIC;

           clk : in  STD_LOGIC;

           rst : in  STD_LOGIC;

           q : out  STD_LOGIC);

end dflipflop;

architecture Behavioral of dflipflop is

begin

process(rst,clk)

                      begin

                                  if(rst='1') then

                                  q<='0';

                                  elsif( clk'event and clk='1') then

                                  q<=d;

                                  end if;

                      end process;

end behavioral;