4-Bit Counter-VERILOG

module rip(c, clr, up_down, q);

    input c;

    input clr;

    input up_down;

    output [3:0] q;

reg [3:0] tmp;

always@(posedge c or  posedge clr)

          begin

          if (clr)

                      tmp = 4'b0000;

          else

                      if (up_down)

                                  tmp = tmp + 1'b1;

                      else

                                  tmp =  tmp - 1'b1;

          end

                                  assign q = tmp;

endmodule