BUNCH: 2011

Thursday, December 29, 2011

DESIGN OF REAL TIME CLOCK USING FPGA

DESIGN OF REAL TIME CLOCK USING FPGA

AIM:

To design a real time clock and demonstrate its working on the FPGA board.

APPARATUS REQUIRED:

· PC

· xilinx ISE software

PROCEDURE:

· Open Xilinx ISE software.

· Open file new project.

· Enter default data on the dialog box.

· Select new source from project.

· Select verilog module.

· Enter file name.

· Specify the input & output ports.

· Type the output syntax.

· Select implementation constraint file.

· select file name.

· Select assign package pins & assign it.

· Then on the kit & implement the design.

· In generate program file go to configuration device choose that and close it.

· Select generate PROM file & click it & generate it.

· Then go to properties & change CLK to JTAG CLK.

PROGRAM:

module RTC (clk,rst,mode,set,sl,atoh);

input clk; //system clk

input rst;//reset

input [1:0] mode;//mode selection

input [7:0] set;//set value

input [5:0] sl;//segment selection

output [7:0] atoh;//segment display control data

reg[5:0] sl;

reg[7:0] atoh;

reg[26:0] sig2;

reg[19:1] sig3;

reg[7:0] ssdigit1, ssdigit2, ssdigit3, ssdigit4, ssdigit5, ssdigit6;

reg[3:0] digit1, digit2, digit3, digit4, digit5, digit6;

always @ (posedge clk (or) negedge rst)

begin

if(rst==1’b0)begin

sig1=0;

sig3=0;

digit1=0;

digit2=0;

digit3=0;

digit4=0;

digit5=0;

digit6=0;

end

else begin

if(mode==2’b00) begin // hours

if(set[7:4]<=4’b0010)

digit1=set[7:4];

if(set[3:0]<=4’b1001)

digit2=set[3:0];

else

digit2=0;

end

else if(set[7:4]==4’b0010)begin

if(set[3:0]<=4’b0011)begin

digit1=set[7:4];

digit2=set[3:0];

end

else begin

digit1=0;

digit2=0;

end

else begin

digit1=0;

digit2=0;

end

else if(mode==2’b01)begin

if(set[7:4]==4’b0101)

digit3=set[7:4];

if(set[3:0]<=4’b1001)

digit4=set[3:0];

else

digit4=0;

end

else begin

digit3=0;

digit4=0;

end

else if(mode==2’b10)begin

if(set[7:4]<=4’b0101)begin

digit5=set[7:4];

if(set[3:0]<=4’b1001)

digit6=set[3:0];

else

digit6=0;

end

else begin

digit5=0;

digit6=0;

end

else begin

sig2=sig2+1;

case(sig2[24:23])

2’b00:begin

digit6=digit6+1;

if(digit6>4’b1001)begin

digit6=4’b0000;

digit5=digit5+1;

if(digit5>4’b0101)begin

digit5=4’b0000;

digit4=digit4+1;

if(digit4>4’b1001)begin

digit4=4’b0000;

digit3=digit3+1;

if(digit3>4’b0101)begin

digit3=4’b0000;

digit2=digit2+1;

if(digit2>4’b1001)begin

digit2=4’b0000;

digit1=digit5+1;

end

if((digit1>=4’b0010)&( digit2>=4’b0100))begin

digit1=4’b0000;

digit2=4’b0000;

end

sig3=[24:23]=2’b01;

end

2’b11:begin

if(sig2[22:19]==4’b1001)

sig2=0;

end

default:begin

end

end case

end

sig3=sig3+1;

case(sig3[17:15])

3’b000:begin

S1=6’b111110;

Case(digit1)

4’b0000:ssdigit1=8’b00111111;

4’b0001:ssdigit1=8’b00000110;

4’b0010:ssdigit1=8’b01011011;

default:ssdigit1=8’b00000000;

end case

atoh=ssdigit1;

end

3’b001:begin

s1=6’b111101;

case(digit2)

4’b0000:ssdigit2=8’b00111111;

4’b0001:ssdigit2=8’b00000110;

4’b0010:ssdigit2=8’b01011011;

4’b0011:ssdigit2=8’b01001111;

4’b0100:ssdigit2=8’b01100110;

4’b0101:ssdigit2=8’b01101101;

4’b0110:ssdigit2=8’b01111101;

4’b0111:ssdigit2=8’b00000111;

4’b1000:ssdigit2=8’b01111111;

4’b1001:ssdigit2=8’b01101111;

default:ssdigit2=8’b00000000;

end case

atoh=ssdigit2;

end

3’b011:begin

s1=6’b111011;

case(digit3)

4’b0000:ssdigit3=8’b00111111;

4’b0001:ssdigit3=8’b00000110;

4’b0010:ssdigit3=8’b01011011;

4’b0011:ssdigit3=8’b01001111;

4’b0100:ssdigit3=8’b01100110;

4’b0101:ssdigit3=8’b01101101;

default:ssdigit3=8’b00000000;

end case

atoh=ssdigit3;

end

3’b100:begin

s1=6’b110111;

case(digit4)

4’b0000:ssdigit4=8’b00111111;

4’b0001:ssdigit4=8’b00000110;

4’b0010:ssdigit4=8’b01011011;

4’b0011:ssdigit4=8’b01001111;

4’b0100:ssdigit4=8’b01100110;

4’b0101:ssdigit4=8’b01101101;

4’b0110:ssdigit4=8’b01111101;

4’b0111:ssdigit4=8’b00000111;

4’b1000:ssdigit4=8’b01111111;

4’b1001:ssdigit4=8’b01101111;

default:ssdigit4=8’b00000000;

end case

atoh=ssdigit4;

end

3’b110:begin

s1=6’b101111;

case(digit5)

4’b0000:ssdigit5=8’b00111111;

4’b0001:ssdigit5=8’b00000110;

4’b0010:ssdigit5=8’b01011011;

4’b0011:ssdigit5=8’b01001111;

4’b0100:ssdigit5=8’b01100110;

4’b0101:ssdigit5=8’b01101101;

default:ssdigit5=8’b00000000;

end case

atoh=ssdigit5;

end

3’b111:begin

s1=6’b011111;

case(digit6)

4’b0000:ssdigit6=8’b00111111;

4’b0001:ssdigit6=8’b00000110;

4’b0010:ssdigit6=8’b01011011;

4’b0011:ssdigit6=8’b01001111;

4’b0100:ssdigit6=8’b01100110;

4’b0101:ssdigit6=8’b01101101;

4’b0110:ssdigit6=8’b01111101;

4’b0111:ssdigit6=8’b00000111;

4’b1000:ssdigit6=8’b01111111;

4’b1001:ssdigit6=8’b01101111;

default:ssdigit6=8’b00000000;

end case

atoh=ssdigit6;

end

end case

end

end module

UCF:

NET”clk” LOC=”A8”;

NET”rst” LOC=”j6”;

NET”atoh<0>” LOC=”p8”;

NET”atoh<1>” LOC=”p10”;

NET”atoh<2>” LOC=”p9”;

NET”atoh<3>” LOC=”p6”;

NET”atoh<4>” LOC=”p8”;

NET”atoh<5>” LOC=”p5”;

NET”atoh<6>” LOC=”p3”;

NET”atoh<7>” LOC=”p11”;

NET”s1<0>” LOC=”p1”;

NET”s1<1>” LOC=”p2”;

NET”s1<2>” LOC=”p7”;

NET”s1<3>” LOC=”r4”;

NET”s1<4>” LOC=”r11”;

NET”s1<5>” LOC=”r18”;

RESULT:

Thus the design of real time clock is done and its working is verified

SERIAL ADDER AND SUBTRACTOR

AIM:

To design and stimulate the pipelined serial adder and subtractor to add or subtract 8 number of size 12 bits each in 2’s complement.

APPARATUS REQUIRED:

· PC

· Xilinx ISE software

PROCEDURE:

· Open Xilinx ISE software.

· Open file new project.

· Enter default data on the dialog box.

· Select new source from project.

· Select verilog module.

· Enter file name.

· Specify the input & output ports.

· Type the output syntax.

· Select synthesis/implementation in source window.

· In the process window select synthesis–XST.

· Select view synthesis report and note down the final report.

· Select view RTL synthesis the schematic and check the block diagram.

· Select stimulate behavioral modal and give the input and output Waveform.

SERIAL ADDER USING 2’S COMPLEMENT:

module sadd (sum,carry);

output [11:0] sum;

output [2:0] sum;

reg [11:0] sum;

reg[2:0] carry;

//8 input each of 12 bits

reg [11:0] in1=12’b000000000001;// 001

reg [11:0] in 2=12’b000000000001;// 001

reg[11:3] in 3=12’b000000000001;// 001

reg[11:0] in 4=12’b000000000001;// 001

reg[11:0] in 5=12’b000000000010;// 002

reg[11:0] in 6=12’b000000000010;// 002

reg[11:0] in 7=12’b000000000010;// 002

reg[11:0] in 8 12’b000000000010;// 002.

// temporary signals

reg[12:0] a1,a2,a3,a4,a5,a6,a7,a8;

reg[12:0] temp=13’b1000000000000;

reg[15:0] temp1=16’b1000000000000000;

reg[2:0] carry=3’b000;

reg[14:0] c=15’b000000000000000;

reg[14:0] reg=15’b0000000000000000;

reg[13:0]bit0,bit1,bit2,bit3,bit4,bit5,bit6,bit6,bit7,bit8,bit9,bit10,bit11,bit12;

always@(temp,in1,in2,in3,in4,in5,in6,in7,in8,a1,a2,a3,a4,a5,a6,a7,a8,temp1,c, reg, bit0, bit1, bit12)

begin

//CONVERTING INPUT DATA INTO 2’S COMPLEMENT DATA

a1<=temp-in1; //2’s complement of in1

a2<=temp-in2; //2’s complement of in2

a3<=temp-in3; //2’s complement of in3

a4<=temp-in4; // 2’s complement of in4

a5<=temp-in5; //2’s complement of in5

a6<=temp-in6; //2’s complement of in6

a7<=temp-in7; //2’s complement of in7

a8<=temp-in8; //2’s complement of in8.

//ADDING 2’S COMPLEMENT DATA SERIALLY

bit0<=a1[0]+a2[0]+a3[0]+a4[0]+a5[0]+a6[0]+a7[0]+a8[0];

bit1<=a1[1]+a2[1]+a3[1]+a4[1]+a5[1]+a6[1]+a7[1]+a8[1];

bit2<=a1[2]+a2[2]+a3[2]+a4[2]+a5[2]+a6[2]+a7[2]+a8[2];

bit3<=a1[3]+a2[3]+a3[3]+a4[3]+a5[3]+a6[3]+a7[3]+a8[3];

bit4<=a1[4]+a2[4]+a3[4]+a4[4]+a5[4]+a6[4]+a7[4]+a8[4];

bit5<=a1[5]+a2[5]+a3[5]+a4[5]+a5[5]+a6[5]+a7[5]+a8[5];

bit6<=a1[6]+a2[6]+a3[6]+a4[6]+a5[6]+a6[6]+a7[6]+a8[6];

bit7<=a1[7]+a2[7]+a3[7]+a4[7]+a5[7]+a6[7]+a7[7]+a8[7] ; ;

bit8<=a1[8]+a2[8]+a3[8]+a4[8]+a5[8]+a6[8]+a7[8]+a8[8];

bit9<=a1[9]+a2[9]+a3[9]+a4[9]+a5[9]+a6[9]+a7[9]+a8[9];

bit10<=a1[10]+a2[10]+a3[10]+a4[10]+a5[10]+a6[10]+a7[10]+a8[10];

bit11<=a1[11]+a2[11]+A3[11]+a4[11]+a5[11]+a6[11]+a7[11]+a8[11];

bit12<=a1[12]+a2[12]+a3[12]+a4[12]+a5[12]+a6[12]+a7[12]+a8[12];

//CONCANTENATE CARRY AND LOWER BITS

c<={bit12[0],bit11[0],bit10[0],bit9[0],bit8[0],bit7[0],bit6[0],bit5[0],bit4[0],

bit3[0],bit2[0],bit1[0],bit0[0]};

//again 2’s complement the adder data to get original value

reg<=temp1-c;

sum<=reg[11:0];

carry<=reg[14:12];

end

end module.

SERIAL SUBTRACTOR:

module Ssub(reg,sign);

output[14:0] reg;

output sign;

reg[14:0] reg;

reg sign;

//8 INPUTS OF 12 BITS EACH

reg[11:0] in 1=12’b000000001111; //00F

reg[11:0] in 2=12’b000000000001; //001

reg[11:0] in 3=12’b000000000001; //001

reg[11:0] in 4=12’b000000000001; //001

reg[11:0] in 5=12’b000000000001; //001

reg[11:0] in 6=12’b000000000001; //001

reg[11:0] in 7=12’b000000000001; //001

reg[11:0] in 8=12’b000000000001; //001

//TEMPORARY SIGNALS

reg[15:0] temp=16’b100000000000000000;

reg[16:0] temp1=17’b10000000000000000;

reg[3:0] bit0,bit1,bit2,bit3,bit4,bit5,bit6,bit7,bit8,bit9,bit10,bit11;

reg[1:0] bit0,bit1,bit2,bit3,bit4,bit5,bit6,bit7,bit8,bit9,bit10,bit11,bit12,bit13,

bit14;

reg[15:0] c,reg1;

reg[14:0] store,t1;

//ADDING DATA IN 2 TO IN 8 SERIALLY

bit0<=in 2[0]+in 3[0]+in 4[0]+in 5[0]+in 6[0]+in 7[0]+in 8[0];

bit1<=in 2[1]+in 3[1]+in 4[1]+in 5[1]+in 6[1]+in 7[1]+in 8[1]+bit0[3:1];

bit2<=in 2[2]+in 3[2]+in 4[2]+in 5[2]+in 6[2]+in 7[2]+in 8[2]+bit1[3:1];

bit3<=in 2[3]+in 3[3]+in 4[3]+in 5[3]+in 6[3]+in 7[3]+in 8[3]+bit2[3:1];

bit4<=in 2[4]+in 3[4]+in 4[4]+in 5[4]+in 6[4]+in 7[4]+in 8[4]+bit3[3:1];

bit5<=in 2[5]+in 3[5]+in 4[5]+in 5[5]+in 6[5]+in 7[5]+in 8[5]+bit4[3:1];

bit6<=in 2[6]+in 3[6]+in 4[6]+in 5[6]+in 6[6]+in 7[6]+in 8[6]+bit5[3:1];

bit7<=in 2[7]+in 3[7]+in 4[7]+in 5[7]+in 6[7]+in 7[7]+in 8[7]+bit6[3:1]

bit8<=in 2[8]+in 3[8]+in 4[8]+in 5[8]+in 6[8]+in 7[8]+in8[8]+bit7[3:1];

bit9<=in 2[9]+in 3[9]+in 4[9]+in 5[9]+in 6[9]+in 7[9]+in 8[9]+bit8[3:1];

bit10<=in 2[10]+in 3[10]+in 4[10]+in 5[10]+in 6[10]+in 7[10]+in8[10]+bit9[3:1];

bit11<=in 2[11]+in 3[11]+in 4[11]+in 5[11]+in6[11]+in7[11]+in8[11]+bit10[3:1];

//CONCANTENATE CARRY AND LOWER BIT

Store<={bit11[0],bit10[0],bit9[0],bit8[0],bit7[0],bit6[0],bit5[0],bit4[0],bit3[0]

bit2[0],bit1[0],bit0[0]};

p1<=temp-store;

//ADDING DATA IN 1 AND P1 SERIALLY

bits[0]<=in 1[0]+p1[0];

bits[1]<=in 1[1]+in p1[1]+bits0[1];

bits[2]<=in 1[2]+in p1[2]+bits1[1];

bits[3]<=in 1[3]+in p1[3]+bits2[1];

bits[4]<=in 1[4]+p1[4]+bits3[1];

bits[5]<=in 1[5]+p1[5]+bits4[1];

bits[6]<=in 1[6]+p1[6]+bits5[1];

bits[7]<=in 1[7]+p1[7]+bits6[1];

bits[8]<=in 1[8]+p1[8]+bits7[1];

bits[9]<=in 1[9]+p1[9]+bits8[1];

bits[10]<=in 1[10]+p1[10]+bits9[1];

bits[11]<=in 1[11]+p1[11]+bits10[1];

bits[12]<=1’b[0]+p1[12]+bits11[1];

bits[13]<=1’b[0]+p1[13]+bits12[1];

bits[14]<=1’b[0]+p1[14]+bits13[1];

//CONCANTENATE CARRY AND LOWER BITS

C<={bits14,bits13[0],bits12[0],bits11[0],bits10[0],bits9[0],bits8[0],bits7[0],

bits6[0],bits5[0],bits4[0],bits3[0],bits2[0],bits1[0],bits0[0]};

if(c[15]==1’b1)begin

sign=1’b0;

reg<=c[14:0];

end

else begin

sign<=1’b1;

reg1<=temp1-c;

reg<=reg1[14:0];

end

end module.

RESULT:

Thus the serial adder and subtractor is designed and simulated.

MULTIPLICATION OF 2-SIGNED 8-BIT NUMBERS IN 2’S COMPLEMENT

AIM:

To multiply two signed 8-bit numbers using 2’s complement.

APPARATUS REQUIRED:

· PC

· Xilinx ISE software.

PROCEDURE:

· Assign the clock input to clock,and set the values to multiplier and multiplicand.

· Check the multiplier and multiplicand are positive then do the successive addition for product.

· Otherwise multiplier is positive and multiplicand is negative then do the successive addition.MSB is replaced by 1 instead of zero.

· If multiplier is negative and multiplicand is positive then take 2’s complement of multiplicand and do the successive addition for that multiplicand.

· If both multiplier and multiplicand are negative then take 2’s complement of multiplicand and do successive addition but MSB is replaced by 1 instead of zero.

PROGRAM:

Module mul-8- bit (clk,mr,md,p);

input clk;

input [7:0] Mr.;

input [7:0] md;

Output [15:0] p;

Reg [4:0] sig=5’b 00000;

reg [8:0]md=9’b 000000000;

reg [16:0]qu=17’b00000000000000;

reg [16:0]pq=17’b00000000000000000;

always @ (posedge clk)

begin,

if (mr[7]=1’b0)+(md[7]=1’b0) begin

if (sig<= 5’b00000) begin

qo<={9’b000000000,mr};

end

else if (qo[0]=I’bo) begin

pq<=qo;

end

qo<={I’bo,pq[16:17]};

end

else begin

p<=qo [15:0];

sig <=5,b00000;

end

sig <=sig+1;

end

else if((mf[7]==ib0)+(md[7]==ib1))

begin

if (sig==5’b00000)begin

qo<={9’b000000000,mr};

end

else if (sig<=5’b10000)begin

if(qo[[0]==1’b1)begin

pq<=qo+{1’b1,md,8’b00000000};

end

else if(qo[0]==1’b0)begin

pq<=qo;

end

qo=<{1’bo,pq(16:1)};

end

else begin

p<=qo[15:0]+{md com [7:0];8’b 00000000};

sig<=5’b00000;

end

sig<=sig+1;

end

else begin

md com<=100000000-{1’bo,md};

if(sig==5’b 00000}begin

qo<={9’b 000000000,mr};

end

else if (sig<=5’b 10000) begin

if(qo[0]==1’b1)begin

pq<=qo+{1’b1,md,8’b 00000000};

end

else if (qo[0]==1’bo) begin

pq<=qo;

end

qo<={1’b1,pq[16:1]};

end

else begin

p<=qo[15:0]+{md co [7:0],8’b 00000000};

sig<=5’b 00000;

end

sig<=sig+1;

end

end module

UCF:

NET “CLK” LOC=”A8”;

NET”md<0>” LOC=”J11”;

NET”md<1>” LOC=”j12”;

NET” md<2> LOC=”k4”;

NET” md<3> LOC=”m3”;

NET” md<3> LOC=”m7”;

NET”md<5>” LOC=”m13”;

NET”md<6>” LOC=”n3”;

NET”md<7>” LOC=”n11”;

NET”mr<0>” LOC=”r3”;

NET”mr<1>” LOC=”n1”;

NET”mr<2>” LOC=”g12”;

NET”mr<3>” LOC=”t2”;

NET”mr<4>” LOC=”t7”;

NET”mr<5>” LOC=”t9”;

NET”mr<6>” LOC=”t12”;

NET”mr<7>” LOC=”t14”;

NET”P<0>” LOC=”p14”;

NET”P<1>” LOC=”t13”;

NET”P<2>” LOC=”r13”;

NET”P<3>” LOC=”p13”;

NET”p<4>” LOC=”n12”;

NET”P<5>” LOC=”n9”;

NET”P<6>” LOC=”P12”;

NET”P<7>” LOC=”n10”;

NET”P<8>” LOC=”r10”;

NET”P<9>” LOC=”t8”;

NET”P<10>” LOC=”r6”;

NET”P<11>” LOC=”t5”;

NET”P<12>” LOC=”t4”;

NET”P<13>” LOC=”k3”;

NET”P<14>” LOC=”r2”;

NET”P<15>” LOC=”r1”;

RESULT:

Thus the multiplication of 2 signed 8-bit numbers using 2’s complement is done and the output is verified.